Flash memory devices are used in a variety of products including cellular phones and set-top boxes. Flash memory devices are flexible because the end user can program microcode and software at the last step in the manufacturing process. The ability to program at the last cycle in the manufacturing process enables the manufacturer to save money and cycle design time. Flash memory devices offer a wide variety of advantages including user flexibility and a variety of configurations; however, flash memory devices have some inherent disadvantages including slower speeds of data access than conventional volatile memories such as dynamic random access memory DRAM and static random access memory SRAM. Flash memory devices typically operate at maximal data access speeds of 45 to 50 MHz. Conventional volatile memories such as DRAM and SRAM currently operate much faster in a variety of applications. Flash memory is currently proposed for integration with digital signal processors DSPs on the same substrate for use in embedded applications. However, DSPs operate at system clock frequencies in excess of 100 MHz and the slower access rate of floating gate memory arrays are a significant limitation. Therefore, the speeds of flash memories have to increase to reduce DSP bottlenecks.
In addition to the slower speeds of access in floating gate arrays, flash memories currently do not offer random access capability at a high speed. Typically, a page mode access is used which further contributes to inefficient operation. A need exists for a stream-lined pipelined architecture to increase the speed and throughput of flash memory while maintaining random access.